1. Field of the Invention
Example embodiments of the present invention relate to a semiconductor memory device, and more particularly to a semiconductor memory device capable of generating data of various patterns in a test mode.
2. Description of the Related Art
Generally, a memory device is used for temporarily or permanently storing data and/or commands which are used in computers, communication systems, image processing systems, and the like. The memory device includes semiconductor memory devices, tapes, magnetic discs, optical discs, etc. Presently, the semiconductor memory device is the most widely used among the various memory devices.
According to a data storage method, these semiconductor memory devices may be categorized into dynamic random-access memory (DRAM), static random-access memory (SRAM), flash memory, and read-only memory (ROM). Storage capacities and operating speeds of these semiconductor memory devices are being rapidly increased.
In order to produce a semiconductor memory device, a semiconductor circuit design process, a manufacturing process, and a test process are sequentially performed. The test process determines an increase or decrease in product reliability. An external test device is configured to write a predetermined test pattern to a cell of the semiconductor memory device; the written test pattern is then read. By comparing the predetermined test pattern with the read test pattern, it may be determined whether or not the tested cell is defective.
The external test device provides an input test pattern and an external clock signal to the semiconductor memory device, and receives the read test pattern from the semiconductor memory device. The external test device compares the input test pattern and the read test pattern to determine whether or not the corresponding cell of the semiconductor memory device is defective.
Nowadays, a double data rate (DDR) mode is adapted in the semiconductor memory device. In the DDR mode, data transfers are performed two times in one clock cycle to increase data transfer rate without increasing a frequency of the external clock signal. In addition, a quadruple data rate (QDR) mode performing four data transfers in one clock cycle, and an octuple data rate (ODR) mode performing eight data transfers in one clock cycle are being researched.
Generally, test devices are developed more slowly than semiconductor memory devices. While the operation speed of semiconductor memory devices continues to rapidly increase to levels higher than 500 MHz, the operation speed of test devices continues to lag.
For example, when a clock frequency of a test device is only about 250 MHz, and a clock frequency of a semiconductor memory device is about 500 MHz, a common clock frequency for testing the semiconductor memory device is downwardly adjusted to the clock frequency of the test device. Moreover, a test device for a semiconductor memory device is very expensive. Thus, it is not easy to develop a new test device for performing a test of a new semiconductor memory device.
A conventional semiconductor memory device includes a frequency multiplier to double a frequency of an external clock signal in a test mode. For example, an exclusive-or (XOR) gate or a phase-locked loop (PLL) doubles the frequency of the external clock signal and generates an internal clock signal having an increased frequency to supplement a slow operation speed of a test device.
However, if a frequency of a clock signal is doubled, but a transfer speed (that is, a bit rate) of the test device is not increased, a testing speed of a semiconductor memory device may suffer. Accordingly, a need remains for a semiconductor memory device that can be tested at high speeds notwithstanding a low-speed tester.